Published January 1, 1993
by Ablex Publishing .
Written in English
|The Physical Object|
|Number of Pages||208|
The author highlights the inherent difficulties encountered with the mechanical probe and testability design approaches for functional and internal fault testing and shows how contactless testing might resolve many of the challenges associated with conventional mechanical wafer testing. The techniques described in this book address the increasing demands for internal access of the logic state of a node within a chip under test:Cited by: 1. The book VLSI Fault Modeling and Testing Techniques, is published by Intellect Ltd. VLSI Fault Modeling and Testing Techniques, Zobrist The Chicago Distribution Center has reopened and is fulfilling orders. VLSI testing. This book covers the spectrum of the testing problem. Areas covered include fault modeling, test generation, fault simulation, memory testing, design for testability, testability measures, PLA testing, and test equipment. ISBN: OCLC Number: Description: vii, pages: illustrations ; 24 cm. Contents: 1. Physical Fault Modeling and Simulation for VLSI MOS Circuits / Mona E. Zaghloul Designing CMOS Gates to Test Open Faults / R. Rajsuman Testing Bridging Faults in VLSI / R. Rajsuman Built-in Self-Test Techniques for Programmable .
Realistic fault modeling for VLSI testing. Share on. Author: physical characteristics and may be significantly different from the simplistic defect models assumed by typical fault modeling techniques. In the tutorial an overview of the actual mechanisms causing processing defects, and the defects' electrical manifestations will be discussed. TESTING OF VLSI CIRCUITS. Introduction to testing – Faults in Digital Circuits – Modelling of faults – Logical Fault Models – Fault detection – Fault Location – Fault dominance – Logic simulation – Types of simulation – Delay models – Gate Level Event – . A Glossary of Fault Models 61 toggle coverage, are also used although these do not conform to any specific fault model . Branch Fault: This fault is modeled at the behavioral level where the circuit function is described in a programming language. A branch fault affects a branch statement and causes it to branch to an incorrect destination. Fault Equivalence. ■Number of fault sites in a Boolean gate circuit = #PI + #gates + # (fanout branches). ■Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2. ■If faults f1 and f2 are equivalent then the corresponding faulty functions are Size: KB.
A selection of delay testing issues and test techniques such as delay fault simulation, test generation, design for testability and synthesis for testability are also covered. Delay Fault Testing for VLSI Circuits is intended for use by CAD and test engineers, researchers, tool developers and graduate students. • The fault can be at an input or output of a gate • Example: NAND gate has 3 fault sites () and 6 single stuck-at faults a b 1 1 z 1 (0) 1 Test vector for a s-a-0 fault File Size: KB. VLSI Test Principles and Architectures Ch. 8-Memory Testing &BIST -P. 11 RAM Fault Models: CF Coupling Fault (CF) A coupling fault (CF) between two cells occurs when the logic value of a cell is influenced by the content of, or operation on, another cell. State Coupling Fault (CFst) – Coupled (victim) cell is forced to 0 or 1 if couplingFile Size: KB. Delay Fault Testing for VLSI Circuits. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of this book, Angela Krstic and Tim Cheng, have personally contributed to this research. Now they do an even greater service to the profession by.